1. Field of the Invention
This invention relates to a converting circuit and, more particularly, to a time to digital converting circuit in which clock pulses are gated by time signals to make a pulse train which is proportional to the time signals and the pulse train is counted to provide digital information.
2. Description of the Prior Art
In the prior art, where clock pulses are gated by time signals having arbitrary pulse widths and, then, the gated clock pulse train is counted by a scaler, a counted value or a digital value which is proportional to the time signals is obtained. In the process of the gating operation and the counting operation, the phase of the clock pulse at which the gate is finally closed in the gating operation is not necessarily kept definite with reference to the gating operation so that the wave form of the last clock pulse is liable to assume an uncertain form. The uncertain form of a clock pulse affects the operation in a first stage binary in the counting operation and it is considered to induce an odd-even unbalance phenomena of the binary circuit. The odd-even unbalance phenomena of the binary circuit is referred to, in this invention, as a phenomena in which variety in counting of clock pulses appears every other channel due to the odd-even unbalance of a binary.
The odd-even unbalance phenomena in the counting result is considered to originate from the fact that the unbalance characteristics of triggers meet with uncertain pulses generated by gate operations under a condition (i) the first stage binary itself has unbalance characteristics against the trigger sensitivity toward the odd direction as well as the even direction, a condition (ii) unbalance is induced in the odd-even characteristics of a trigger according to the unbalance in the load of the binary and a condition (iii) the output voltage or current affects trigger pulses due to the binary operation and the trigger pulses assume distortions in the wave-form in every other pulse due to induction from a binary so that odd-even characteristics are unbalanced.
In order to resolve the odd-even unbalance phenomena, in the prior art, as a first countermove, the counting speed of a scaler is reduced in the operation, as a second countermove, the gated clock pulses are forced to pass through a shaping circuit in order not to ultimately turn the clock pulse to uncertain pulse and, as a third countermove, an arrangement in which the binary operation does not affect trigger pulses and wires are shielded and grounded completely, is provided.
Since the higher the counting speed, the larger the odd-even unbalance phenomena in general, reducing the counting speed is appreciated as effective and, therefore, the first countermove is recognized to be advantageous. However, even though effectiveness in the second countermove and the third countermove can be expected to some extent, a full settlement to the odd-even unbalance phenomena is almost difficult. Thus, in many cases, the performance of the counting circuit is restricted due to the reduction of the counting speed of the binary to 1/2 to 1/3 of the maximum counting speed of the binary itself depending on the first countermove.